Formation of metal-oxide-semiconductor field-effect transistors (MOSFETs) requires the introduction of dopants into, e.g., a silicon (Si) substrate to define source and drain regions. Dopants are also introduced into a gate material, such as polycrystalline silicon (polysilicon), to achieve a desired conductivity. Dopants disposed in source, drain, and gate (S/D/G) regions are activated by a heat treatment to provide the needed electrical characteristics. For good-quality n-type MOS (NMOS) devices, dopant activation is typically performed at a high temperature, e.g., at least 1000° C. for 5 seconds, to avoid polysilicon depletion effects. A gate in which the polysilicon is depleted has a non-uniform distribution of dopants, with a relatively low concentration of dopants near an interface with a gate dielectric. This depletion region can result in reduced gate capacitance during device operation, resulting in a lower transistor drive current.
Activation of dopants in regions defined on substrates with strained layers, such as strained Si, presents a challenge. Strained Si substrates include a thin strained Si layer having a thickness of, e.g., 40–400 Å. The strained Si layer is disposed over a second material, e.g., a relaxed SiGe layer. A compressively strained SiGe layer may be disposed above or below the strained Si layer. These layer structures may make it difficult to maintain shallow source/drain junctions in, for example, complementary MOS (CMOS) devices, especially when the strained Si/SiGe substrate is subjected to high temperatures. This difficulty arises from the different diffusion rates of dopants in SiGe and in Si. For example, arsenic (As) may diffuse much more rapidly in SiGe than in Si at temperatures significantly above 900° C. and/or times significantly above 30 seconds. This rapid diffusion leads to deeper source/drain junctions in NMOS transistors fabricated on strained-Si/SiGe substrates and/or excessive lateral diffusion of dopants beneath the gate, i.e., into the channel region. Because of the diffusion of As into a channel of the NMOS transistor, the transistor has a high off current (Ioff) and it becomes more difficult to turn off.
In alternative structures, the second material over which the strained layer is disposed may be e.g., a bulk semiconductor substrate, or an insulating material. Here, too, it may be difficult to maintain shallow source/drain junctions or prevent excessive lateral diffusion of dopants, especially when the strained structures are subjected to high temperatures. This difficulty arises from the different diffusion rates of dopants in strained layers in comparison to bulk, non-strained materials. For example, boron diffuses faster through strained Si than through bulk Si.
A possible solution is to perform the S/D/G dopant activation at a restricted time and temperature (e.g., 900° C. for 30 sec). However, these restricted parameters may lead to unacceptable polysilicon depletion effects.